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SPARC 3.6 GHz Processor: A 16-Core, 128 Threaded SoC

Tuesday, Aug 13, 2013 6:30p

of Silicon Valley Presents:

SPARC 3.6 GHz Processor:
a 16-core, 128 threaded SoC

Date: Tuesday, August 13, 2013
Speaker: Jason Hart, Senior Principal Hardware Engineer, Oracle Corporation
Time : 6:30 PM (PT) Networking/Refreshments, 7:00 PM Presentation
Location: Cadence / Bldg 10, 2655 Seely Ave, San Jose, Ca ( map )

The 3.6 GHz T5 processor is Oracle's next- generation CMT Sparc processor implemented in TSMC's 28nm process with 1.5 billion transistors. Significant performance improvements
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Location & Nearby Info
Cadence Design Systems, Inc.
E Trimble Rd and Montague Expy
San Jose, CA 95134
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