We regret to inform you that Zvents.com is closing its doors October 31st, 2014. We’re proud to have served the community for so long, but business pressures have forced us to make the difficult decision to close down Zvents.com and the Zvents Media Network. Thank you for supporting us over the years. For more on the closure of Zvents.com see this page.
Home | Register | Log In

San Jose, CA

   [change my location]
  • Print
  • Calendar
  • Share
Img_phold_gen_primary_no_add
Age Suitability None Specified
Category Other
Tags seminars

IC Layout Design and Verification

Monday, Nov 11, 2013 6:00p

This is one the best IC Layout training programs in the industry. It is part 2 of a 2 course series that covers semiconductor process technologies from 23nm CMOS to 0.35um BCD and explores Analog, Mixed-Signal and RF layout skills. Instructors are seasoned engineers with deep understanding of physical design, class assignments and practice examples are realistic and are taken from actual design projects. Duration of this training program is 12 weeks.

Created by eventbrite | Claim this event

Tickets
eventbrite Check Site Buy Now
Location & Nearby Info
Silicon Valley Technical Institute
1762 Technology Dr.
San Jose, CA 95110
(408) 573-0100
Show nearby:
Reviews & Comments
USER REVIEWS
This event currently has no reviews. Be the first to share your thoughts with others!

Don't Miss This